1. Field of the invention
The present invention relates to a data processor, more particularly, to a data processor which has a branch instruction processing mechanism for executing branch prediction, especially branch prediction for conditional branch instruction, controlled disorder of a pipeline processing so that a multistage pipeline processing mechanism can effectively be operated, and realizes high capability of processing.
2. Description of the Prior Art
FIG. 1 is an example of schematic diagram of a pipeline processing mechanism used for a conventional data processor.
Reference numerals in the figure designate the following elements: 11, instruction fetch stage (IF stage); 12, instruction decoding stage (D stage); 13, operand address calculation stage (A stage); 14, operand fetch stage (F stage); and 15, instruction execution stage (E stage).
The IF stage 11 fetches instruction code from a memory and outputs it to the D stage 12. The D stage 12 decodes the instruction code received from the IF stage 11 and outputs a decoding result to the A stage 13.
The A stage 13 calculates an effective address of operand designated in the instruction code, and then outputs the calculated operand address to the F stage 14. In accordance with the operand address delivered from the A stage 13, the F stage 14 fetches an operand from memory. The fetched operand is delivered to E stage 15. The E stage 15 executes arithmetical operation designated by instruction code for the operand delivered from the F stage 14. It also stores the result of arithmetical operation in memory as required.
The pipeline processing mechanism mentioned above divides the processings designated by each instruction into five stages. By sequentially executing five-step processings, all the designated processing are completed. Each of five processings can be implemented in parallel with each other against different instructions. Ideally, compared to the case where no pipeline processing is executed, the five-stage pipeline processing mechanism mentioned above simultaneously processes five instructions so that an efficient data processor having a maximum of 5-times data processing capability can be provided.
As mentioned above, the pipeline processing mechanism has a possibility of greatly promoting data processing capability of data processors, and thus, is widely made available for achieving high-speed data processing operation.
Nevertheless, even the pipeline processing mechanism still has problems to solve. Actually, instructions are not always processed in ideal conditions. One of these critical problems is the method of executing branch instruction which easily disturbs the sequence of instructions.
The conventional data processor having the pipeline processing mechanism shown in FIG. 1 causes pipeline to be disturbed significantly when executing branch instructions by allowing the IF state 11 to fetch the branch target instruction.
FIG. 2 shows the state of instruction flows through pipeline when branch instructions are executed in the conventional data processor. In FIG. 2, instruction IN 3 and IN 12 are branch instructions. When instruction IN 3 is executed, whole instructions IN 4 through IN 7 under pipeline processing operation are canceled, and as a result, the IF stage 11 starts to process instruction IN 11. If this occurs, the time enough to process four instructions is wasted in the period from the execution of the instruction IN 3 via the E stage 15 to the execution of the instruction IN 11 by the E stage 15. Likewise, the time enough to process four instructions is wasted before executing the instruction IN 12. Only after completing all the pipeline processings for branch instruction, fetching of instruction to be processed after execution of branch instruction is executed by any conventional data processor, thus eventually resulting in the wasted time. The more the number of pipeline processing stages, the more the time being wasted.
To minimize disturbance incurring to pipeline by activation of branch instructions, any conventional data processor executes branch prediction processing by allowing the D stage 12 to predict the branching of conditional branch instruction at the time of decoding instructions and then shifts the destination of instruction to be fetched to the designated branch by means of the IF stage 11 before eventually allowing the E stage 15 to execute the conditional branch instruction.
When the operand to be prefetched by the F stage 14 corresponds to the other operand to be written by E stage 15, the F stage 14 does not prefetch operand from the memory, but it bypasses an operand value to be written by E stage 15, thus saving one time of operation for reading data from the memory.
Normally, efficiency in the pipeline processing operation is promoted by executing branch prediction which allows the decoding stage to predict branching of conditional branch instruction and then allows instruction fetch stage to shift the destination of instruction to be fetched to the designated branch target in advance.
However, when applying a application program in which branching is alternately activated and inactivated by conditional branch instruction, efficiency in the execution of instruction may adversely be affected by branch prediction.
When the entire system is reset or executing condition of program varies, since the branch prediction bit merely is decided by history of the program which was already executed, branch prediction is completely unreliable.
Furthermore, if an external address bus were monitored when monitoring operation of a microprocessor with an external pins of the chip for debugging, if the prediction of branching of the instruction branch prediction mechanism were missed, branching takes place once, which mislead the monitor system as though the operation is back to the original flow by causing branching to occur over again. This makes it difficult for the monitoring system to follow up the flow of instructions.
To solve those technical problems mentioned above, an improved art was proposed by Japanese Patent Application Laid-Open No. 59-183434 (1984). This preceding art has such a configuration that the programmer himself identifies the probability of achieving the branching effect of conditional branch instruction and programming is made to execute ON/OFF control of register for controlling preliminary acquisition of instruction for each instruction. When the register is activated, conditional branch instruction is processed on the assumption that it is supposed to be branched. When the register is inactivated, the conditional branching instruction is processed on the assumption that it is not branched. Nevertheless, the configuration mentioned above obliges programming to sustain extremely heavy load all the time.